1. Field of the Invention
The present invention relates to memory access, and more particularly, to an arbiter that arbitrates access of a multi-bank memory.
2. Description of the Related Art
In an application system supporting a multi-bank memory such as a synchronous dynamic random access memory (SDRAM) or a double data rate (DDR)-SDRAM, a system on chip (SOC) for video or audio requires high memory bandwidth. In order for the SOC to have higher memory bandwidth, increases are needed in arbitration efficiency of a memory bus as well as in system clock speed. That is, in an access arbitration in the multi-bank memory, when masters such as a micro-control unit (MCU) and an ARM core (a microchip of ARM Inc.), for example, access the banks included in the memory, the arbitration should be performed so as to allow the masters to access grants efficiently and perform an interleaving bank arbitration process. The masters transfer information to write data on the memory or to read the data stored in the memory, and to access the banks.
A conventional arbiter uses a simple way to arbitrate the requests of the masters accessing the banks in the memory. That is, in a bank interleaving method, requests that are not accesses to busy banks are detected from pending requests, and access grants are allowed to the masters. The busy bank is a bank performing a read or write operation among the banks in the memory, and the read or write operation is performed during predetermined cycles of the system clock. In addition, in a read/write turn-around time minimizing method, requests that have the same direction as those of the previous access are detected among the pending requests, and these requests are granted. In addition, in a same row access detection method, requests that are to access a row of the memory cell array the same as an active row of the busy bank are detected, and the grants are given to the requests.
Since the memory bank is in the busy state during predetermined cycles of the system clock when the memory bank is accessed, the above memory bank can be accessed again when the bank is released from the busy state. During a time when a certain bank is in the busy state, other banks that are not in busy states are accessed.
FIG. 1A is a view illustrating a conventional accessing method to the multi-bank memory, indicated generally by the reference numeral 100. Referring to FIGS. 1A through 1C, each figure represents a normal case, indicated generally by the reference numerals 100, 120 and 140, respectively. The first case 100 has an overhead cycle, and the second case 120 also has an overhead cycle. Here, it is assumed that the busy state of the bank is maintained for three access times (ATs). The case 100 of FIG. 1A is a case where the bank 0 is accessed again after a 3AT period has elapsed since the first access, and a normal bank interleaving operation is performed without the overhead cycle. In (b) of FIG. 1, a request for accessing bank 0 is generated again within a 1AT period before the busy state of the bank 0 is released, and the access to the bank 0 should be made after passing the overhead cycle of 1AT in order to access the bank 0 after accessing to the bank 1, because the busy state of the accessed bank is maintained for a 3AT period. Like the case 120, in the case 140 there is a request for accessing the bank 0 within a 2AT period before the busy state of the bank 0 is released, and the access to the bank 0 should be made after passing the overhead cycle of the 2AT period. In the conventional method of accessing the multi-bank memory, many overhead cycles happen when the accessing order to the multi-banks is not arbitrated appropriately, thus, the system speed is lowered, and accordingly, the high memory bandwidth required in the application system cannot be satisfied.